Conventional microelectronic devices are packaged in a planar or two-dimensional (2D) surface-mount configuration. In this configuration, the package size (particularly the footprint) is dictated by both the number of and physical dimensions of the integrated circuit (IC) chips or other discrete devices included in the package, as well as the area occupied by the discrete surface-mounted passive components utilized. There is a continuing demand for smaller electronic products that at the same time provide a higher level of functionality. Hence, there is a concomitant demand for higher-performance, smaller-footprint packaged microelectronic devices for use in such products. In response, researchers continue to develop three-dimensional (3D) integration or chip-stacking technologies as an alternative to the conventional 2D format. By implementing 3D integration, multiple die may be “vertically” arranged (in the third dimension) in a single packaged electronic device, with adjacent die communicating by way of 3D (or “vertical”) metal interconnects extending through the thicknesses of the die substrates. Also, 3D integration can enable vertical integration of passives such as capacitors and inductors, thereby reducing overall package size. 3D integration may be done at the wafer level (wafer-to-wafer bonding), the die level (die-to-die bonding), or in a hybrid format (die-to-wafer bonding). 3D packages can provide various advantages, such as shorter signal propagation delay (and thus faster signal processing), lower power consumption, reduced cross-talk, smaller package footprint, smaller device size, and higher input/output (I/O) count and density. Moreover, the different die stacked in the 3D package may be configured to provide different functions. For example, one die may include an active electronic device while another die may include an arrangement of passive components (resistors, capacitors, inductors, etc.), an array of memory modules, or a ground plane that communicates with several interconnects.
The formation of 3D metal interconnects has generally been accomplished by either a “vias first” approach or a “vias last” approach. In the “vias first” approach, the interconnects are formed prior to circuitry fabrication, substrate thinning, and substrate (die or wafer) bonding. In the “vias last” approach, the interconnects are formed after circuitry fabrication, substrate thinning, and substrate bonding. Particularly in the case of the “vias last” approach, the interconnect metal may need to be deposited through more than one layer of material in order for the metal to land on the surface of a contact pad and form a low-resistance electrical coupling with the contact pad. For example, to reach the contact pad the interconnect metal may need to be deposited through a deep via that extends through the entire thickness of one substrate and possibly partially into the thickness of an adjacent substrate where the contact pad is located, as well as through one or more intervening layers between these two substrates such as bonding layers, insulating layers, passivation layers, etc. Moreover, as a result of preceding material addition steps, an etching step (i.e., “bottom-clear” etching) such as deep reactive ion etching (DRIE) is typically required to expose the contact pad prior to the interconnect metallization step. Effective etching and interconnect metallization steps become more challenging as the aspect ratio (i.e., depth-to-diameter) of the vias increases.
In U.S. Pat. No. 8,361,901, titled DIE BONDING UTILIZING PATTERNED ADHESION LAYER; and co-pending International Publication No. WO 2014/004504, titled THREE-DIMENSIONAL ELECTRONIC PACKAGES UTILIZING UNPATTERNED ADHESIVE LAYER; the contents of both of which are incorporated by reference herein in their entireties, these difficulties are addressed by utilizing an adhesive layer as the bonding medium between two substrates. This adhesive layer is deposited on one substrate and patterned to create openings exposing underlying contact pads of the substrate. The two substrates are then bonded together, with the metal pads of the one substrate being aligned with corresponding vias of the other substrate. This approach facilitates the subsequent bottom-clear and interconnect metallization steps.
It would be further desirable to integrate large-area 3D conductive planes in 3D electronic packages. Such conductive planes may be useful, for example, as ground planes, power planes, signal planes, inductor coils or as capacitor electrodes. It would be desirable to integrate such functionality within the footprint and thickness of 3D electronic packages. Currently, wafer-scale conductive planes are difficult to produce due to defect levels, as even one particle could short the plane to an adjacent layer/level. It would thus be desirable to provide methods for fabricating integrated conductive planes that reduce the occurrence of particles and/or are tolerant to particles. More generally, it would be desirable to provide 3D electronic packages featuring integrated conductive planes that perform reliably and effectively, and methods for fabricating such electronic packages.